module adder8_2(cout,sum,clk,cina,cinb,cin,rst_n); always @(posedge clk or negedge rst_n) begin //??8???à?ó
if(!rst_n) begin cout =0; sum =0; end else sum[3:0] = sum1;
{cout,sum[7:4]} = cina[7:4] + cinb[7:4]+ cout1; // {cout,sum[7:0]} = {{{cina[7],cina[7:4]} + {cinb[7],cinb[7:4]}+ cout1},sum1}; end endmodule 测试文件:
module test_adder16_2;
// Inputs
reg clk; reg [7:0] cina; reg [7:0] cinb; reg cin; reg rst_n; // Outputs wire cout; wire [7:0] sum; // Instantiate the Unit Under Test (UUT)
adder8_2 uut ( .cout(cout), .sum(sum), .clk(clk), .cina(cina), .cinb(cinb), .cin(cin), .rst_n(rst_n) ); initial begin
// Initialize Inputs clk = 0; cina = 0; cinb = 0; cin = 0; rst_n=1; #100 rst_n=0; // Wait 100 ns for global reset to finish #200; rst_n=1; // Add stimulus here #100 cina = 8'b0000_0001; cinb = 8'b0000_1111; cin=1'b1; #200 cina = 8'b1111_0001; cinb = 8'b0000_1011; cin=1'b1; #200 cina = 8'b0111_0011; cinb = 8'b0100_1111; cin=1'b1; #200 cina = 8'b1100_1000; cinb = 8'b1000_1111; cin=1'b1; #200 cina = 8'b0001_1000; cinb = 8'b0100_0011; cin=1'b1; #200 cina = 8'b0101_1000; cinb = 8'b0000_1111; cin=1'b1; end always #50 clk = ~clk; endmodule |
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