初始化内存程序转化为JLINK脚本gdbinit | 学步园

圆锥的布袋 2017-05-14

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初始化内存程序转化为JLINK脚本gdbinit

遇到一个新的板子，最先调试是在不用初始iram或者叫垫脚石中调试。不过最终还是要在ddram中。所以就要在脚本中对内存的初始化。

gdbinit有一件也是唯一关键的事是必须做的，就是初始化内存。无论是SDRAM也好，DDRAM也好。只要有程序能初始化的，都是可以将程序转化为脚本。这样就可以程序在内存中调试程序了。

下面以tiny210v2的实例来说明：

1.要先有一个确定能成功初始化的程序，结合提供的测试裸机程序和u-boot揉合而而成的memory.S

#include "s5pv210.h"

// MemControl BL=4, 1Chip, DDR2 Type, dynamic self refresh, force precharge, dynamic power down off

#define DMC0_MEMCONTROL 0x00202400

// MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed

#define DMC0_MEMCONFIG_0 0x20E00323

// MemConfig1

#define DMC0_MEMCONFIG_1 0x20E00323

// TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)

#define DMC0_TIMINGA_REF 0x00000618

// TimingRow for @200MHz

#define DMC0_TIMING_ROW 0x2B34438A

// TimingData CL=3

#define DMC0_TIMING_DATA 0x24240000

// TimingPower

#define DMC0_TIMING_PWR 0x0BDC0343

.globl mem_init

mem_init:

// 1. 设置DMC0 Drive Strength (Setting 2X)

ldr
r0, =ELFIN_GPIO_BASE

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_0DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_1DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_2DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_3DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_4DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_5DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_6DRV_SR_OFFSET]

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_7DRV_SR_OFFSET]

ldr
r1, =0x00002AAA

str
r1, [r0, #MP1_8DRV_SR_OFFSET]

// 2. 初始化PHY DLL

ldr
r0, =APB_DMC_0_BASE

//step 3: PhyControl0 DLL parameter setting, manual 0x00101000

ldr
r1, =0x00101000

str
r1, [r0, #DMC_PHYCONTROL0]

//PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Case

ldr
r1, =0x00000086

str
r1, [r0, #DMC_PHYCONTROL1]

//step 2: PhyControl0 DLL on

ldr
r1, =0x00101002

str
r1, [r0, #DMC_PHYCONTROL0]

//step 4: PhyControl0 DLL start

ldr
r1, =0x00101003

str
r1, [r0, #DMC_PHYCONTROL0]

find_lock_val:

//Loop until DLL is locked

ldr
r1, [r0, #DMC_PHYSTATUS]

and
r2, r1, #0x7

cmp
r2, #0x7

bne
find_lock_val

//Force Value locking

and
r1, #0x3fc0

mov
r2, r1, LSL #18

orr
r2, r2, #0x100000

orr
r2 ,r2, #0x1000

orr
r1, r2, #0x3

str
r1, [r0, #DMC_PHYCONTROL0]

// 3. 初始化DMC0

//step 5: ConControl auto refresh off

ldr
r1, =0x0FFF2010

str
r1, [r0, #DMC_CONCONTROL]

//step 6: MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off

ldr
r1, =DMC0_MEMCONTROL

str
r1, [r0, #DMC_MEMCONTROL]

//step 7: MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed

ldr
r1, =DMC0_MEMCONFIG_0

str
r1, [r0, #DMC_MEMCONFIG0]

//MemConfig1

ldr
r1, =DMC0_MEMCONFIG_1

str
r1, [r0, #DMC_MEMCONFIG1]

//step 8:PrechConfig

ldr
r1, =0xFF000000

str
r1, [r0, #DMC_PRECHCONFIG]

//step 9:TimingAref7.8us//133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)

ldr
r1, =DMC0_TIMINGA_REF

str
r1, [r0, #DMC_TIMINGAREF]

//TimingRowfor //200MHz

ldr
r1, =DMC0_TIMING_ROW

str
r1, [r0, #DMC_TIMINGROW]

//TimingDataCL=4

ldr
r1, =DMC0_TIMING_DATA

str
r1, [r0, #DMC_TIMINGDATA]

//TimingPower

ldr
r1, =DMC0_TIMING_PWR

str
r1, [r0, #DMC_TIMINGPOWER]

// 4. 初始化DDR2 DRAM

//DirectCmdchip0 Deselect

ldr
r1, =0x07000000

str
r1, [r0, #DMC_DIRECTCMD]

//step 16:DirectCmdchip0 PALL

ldr
r1, =0x01000000

str
r1, [r0, #DMC_DIRECTCMD]

//step 17:DirectCmdchip0 EMRS2

ldr
r1, =0x00020000

str
r1, [r0, #DMC_DIRECTCMD]

//step 18:DirectCmdchip0 EMRS3

ldr
r1, =0x00030000

str
r1, [r0, #DMC_DIRECTCMD]

//step 19:DirectCmdchip0 EMRS1 (MEM DLL on, DQS# disable)

ldr
r1, =0x00010400

str
r1, [r0, #DMC_DIRECTCMD]

//step 20:DirectCmdchip0 MRS (MEM DLL reset) CL=4, BL=4

ldr
r1, =0x00000542

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip0 PALL

ldr
r1, =0x01000000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip0 REFA

ldr
r1, =0x05000000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip0 REFA

ldr
r1, =0x05000000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip0 MRS (MEM DLL unreset)

ldr
r1, =0x00000442

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip0 EMRS1 (OCD default)

ldr
r1, =0x00010780

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip0 EMRS1 (OCD exit)

ldr
r1, =0x00010400

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 Deselect

ldr
r1, =0x07100000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 PALL

ldr
r1, =0x01100000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 EMRS2

ldr
r1, =0x00120000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 EMRS3

ldr
r1, =0x00130000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 EMRS1 (MEM DLL on, DQS# disable)

ldr
r1, =0x00110400

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 MRS (MEM DLL reset) CL=4, BL=4

ldr
r1, =0x00100542

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 PALL

ldr
r1, =0x01100000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 REFA

ldr
r1, =0x05100000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 REFA

ldr
r1, =0x05100000

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 MRS (MEM DLL unreset)

ldr
r1, =0x00100442

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 EMRS1 (OCD default)

ldr
r1, =0x00110780

str
r1, [r0, #DMC_DIRECTCMD]

//DirectCmdchip1 EMRS1 (OCD exit)

ldr
r1, =0x00110400

str
r1, [r0, #DMC_DIRECTCMD]

//ConControlauto refresh on

ldr
r1, =0x0FF02030

str
r1, [r0, #DMC_CONCONTROL]

//PwrdnConfig

ldr
r1, =0xFFFF00FF

str
r1, [r0, #DMC_PWRDNCONFIG]

//MemControlBL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off

ldr
r1, =0x00202400

str
r1, [r0, #DMC_MEMCONTROL]

mov
pc, lr

总体是4大步，都是在设置寄存器的值。关键的是str指令。

2.实际转换一条代码到脚本中

ldr
r0, =ELFIN_GPIO_BASE

ldr
r1, =0x0000AAAA

str
r1, [r0, #MP1_0DRV_SR_OFFSET]

转换成如下一条脚本命令：

#define ELFIN_GPIO_BASE 0xE0200000

#define MP1_0DRV_SR_OFFSET 0x3CC

monitor MemU32 0xE02003CC 0x0000AAAA

(上边的指令就是向0xE02003CC地址处赋值0x0000AAAA)

3.整体转换如下：（此脚本目前只适用于tiny210v2没有在其它板子上测试过,"#"为注释，为的简洁可以去掉）

# connect to the J-Link gdb server
target remote localhost:2331
# Set JTAG speed to 30 kHz
monitor endian little
monitor speed 30
# Reset the target
monitor reset
monitor sleep 10
  
#ddram init
#1. init DMC0 Drive Strength (Setting 2X)
#define ELFIN_GPIO_BASE         0xE0200000
#define MP1_0DRV_SR_OFFSET      0x3CC
monitor MemU32 0xE02003CC 0x0000AAAA
 
#define MP1_1DRV_SR_OFFSET      0x3EC
monitor MemU32 0xE02003EC 0x0000AAAA
 
#define MP1_2DRV_SR_OFFSET      0x40C
monitor MemU32 0xE020040C 0x0000AAAA
 
#define MP1_3DRV_SR_OFFSET      0x42C
monitor MemU32 0xE020042C 0x0000AAAA
 
#define MP1_4DRV_SR_OFFSET      0x44C
monitor MemU32 0xE020044C 0x0000AAAA
 
#define MP1_5DRV_SR_OFFSET      0x46C
monitor MemU32 0xE020046C 0x0000AAAA
 
#define MP1_6DRV_SR_OFFSET      0x48C
monitor MemU32 0xE020048C 0x0000AAAA
 
#define MP1_7DRV_SR_OFFSET      0x4AC
monitor MemU32 0xE02004AC 0x0000AAAA
 
#define MP1_8DRV_SR_OFFSET      0x4CC
monitor MemU32 0xE02004CC 0x00002AAA
 
#2. init PHY DLL
#define APB_DMC_0_BASE          0xF0000000
#define DMC_PHYCONTROL0         0x18
monitor MemU32 0xF0000018 0x00101000
 
#define DMC_PHYCONTROL1         0x1C
monitor MemU32 0xF000001C 0x00000086
 
#define DMC_PHYCONTROL0         0x18
monitor MemU32 0xF0000018 0x00101002
 
#define DMC_PHYCONTROL0         0x18
monitor MemU32 0xF0000018 0x00101003
 
#2.5
#define DMC_PHYSTATUS           0x40
#monitor MemU32 0xF0000040 0x00101003
#read
 
#define DMC_PHYCONTROL0         0x18
monitor MemU32 0xF0000040 0x6B101003
 
#3. init DMC0
#define APB_DMC_0_BASE          0xF0000000
#define DMC_CONCONTROL          0x00
monitor MemU32 0xF0000000 0x0FFF2010
 
#define DMC_MEMCONTROL          0x04
#define DMC0_MEMCONTROL         0x00202400
monitor MemU32 0xF0000004 0x00202400
 
#define DMC_MEMCONFIG0          0x08
#define DMC0_MEMCONFIG_0        0x20E00323  
monitor MemU32 0xF0000008 0x20E00323
 
#define DMC_MEMCONFIG1          0x0C
#define DMC0_MEMCONFIG_1        0x20E00323
monitor MemU32 0xF000000C 0x20E00323
 
#define DMC_PRECHCONFIG         0x14
monitor MemU32 0xF0000014 0xFF000000
 
#define DMC_TIMINGAREF          0x30
#define DMC0_TIMINGA_REF        0x00000618
monitor MemU32 0xF0000030 0x00000618
 
#define DMC_TIMINGROW           0x34
#define DMC0_TIMING_ROW         0x2B34438A
monitor MemU32 0xF0000034 0x2B34438A
 
#define DMC_TIMINGDATA          0x38
#define DMC0_TIMING_DATA        0x24240000
monitor MemU32 0xF0000038 0x24240000
 
#define DMC_TIMINGPOWER         0x3C
#define DMC0_TIMING_PWR         0x0BDC0343
monitor MemU32 0xF000003C 0x0BDC0343
 
#4. init DDR2 DRAM 
#define DMC_DIRECTCMD           0x10
monitor MemU32 0xF0000010 0x07000000
monitor MemU32 0xF0000010 0x01000000
monitor MemU32 0xF0000010 0x00020000
monitor MemU32 0xF0000010 0x00030000
monitor MemU32 0xF0000010 0x00010400
monitor MemU32 0xF0000010 0x00000542
monitor MemU32 0xF0000010 0x05000000
monitor MemU32 0xF0000010 0x05000000
monitor MemU32 0xF0000010 0x00000442
monitor MemU32 0xF0000010 0x00010780
monitor MemU32 0xF0000010 0x00010400
monitor MemU32 0xF0000010 0x07100000
monitor MemU32 0xF0000010 0x01100000
monitor MemU32 0xF0000010 0x00120000
monitor MemU32 0xF0000010 0x00130000
monitor MemU32 0xF0000010 0x00110400
monitor MemU32 0xF0000010 0x00100542
monitor MemU32 0xF0000010 0x01100000
monitor MemU32 0xF0000010 0x05100000
monitor MemU32 0xF0000010 0x05100000
monitor MemU32 0xF0000010 0x00100442
monitor MemU32 0xF0000010 0x00110780
monitor MemU32 0xF0000010 0x00110400
monitor MemU32 0xF0000010 0x0FF02030
monitor MemU32 0xF0000010 0xFFFF00FF
monitor MemU32 0xF0000010 0x00202400
 
 
    
# Setup GDB for faster downloads
#set remote memory-write-packet-size 1024
monitor speed auto
break _start
load
continue