SPI 初始化代码
- stc_gpio_cfg_t GpioInitStruct;
-
- DDL_ZERO_STRUCT(GpioInitStruct);
-
- Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE);
-
- ///< SPI0引脚配置:主机
- GpioInitStruct.enDrv = GpioDrvH;
- GpioInitStruct.enDir = GpioDirOut;
- GpioInitStruct.bOutputVal = TRUE;
- Gpio_Init(CV520_CS_PORT, CV520_CS_PIN, &GpioInitStruct);
- Gpio_Init(CV520_RST_PORT, CV520_RST_PIN, &GpioInitStruct);
- Gpio_Init(W25_CS_PORT, W25_CS_PIN, &GpioInitStruct);
-
- Gpio_Init(SPI0_PORT, SPI0_CLK_PIN, &GpioInitStruct);
- Gpio_SetAfMode(SPI0_PORT, SPI0_CLK_PIN, GpioAf1); ///<配置SPI0_SCK
-
- Gpio_Init(SPI0_PORT, SPI0_MOSI_PIN, &GpioInitStruct);
- Gpio_SetAfMode(SPI0_PORT, SPI0_MOSI_PIN, GpioAf1); ///<配置SPI0_MOSI
-
- GpioInitStruct.enDir = GpioDirIn;
- GpioInitStruct.enPu = GpioPuEnable;
- Gpio_Init(SPI0_PORT, SPI0_MISO_PIN, &GpioInitStruct);
- Gpio_SetAfMode(SPI0_PORT, SPI0_MISO_PIN, GpioAf1); ///<配置SPI0_MISO
-
-
- stc_spi_cfg_t SpiInitStruct;
-
- ///< 打开外设时钟
- Sysctrl_SetPeripheralGate(SysctrlPeripheralSpi0,TRUE);
-
- ///<复位模块
- Reset_RstPeripheral0(ResetMskSpi0);
-
- //SPI0模块配置：主机
- SpiInitStruct.enSpiMode = SpiMskMaster; //配置位主机模式
- SpiInitStruct.enPclkDiv = SpiClkMskDiv8; //波特率：PCLK/2
- SpiInitStruct.enCPHA = SpiMskCphafirst; //第一边沿采样
- SpiInitStruct.enCPOL = SpiMskcpollow; //极性为低
- Spi_Init(SPI_SPI0, &SpiInitStruct);
- ///<请注意根据外部晶振配置宏——[SYSTEM_XTH],如果使用PLL，XTH必须小于24MHz
- static void SystemClkInit_PLL48M_byXTH(void)
- {
- stc_sysctrl_pll_cfg_t stcPLLCfg;
-
- ///< 切换时钟前（根据外部高速晶振）设置XTH频率范围,配置晶振参数，使能目标时钟，此处为SYSTEM_XTH = 8MHz
- Sysctrl_SetXTHFreq(SysctrlXthFreq4_8MHz);
- Sysctrl_XTHDriverCfg(SysctrlXtalDriver3);
- Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384);
- Sysctrl_ClkSourceEnable(SysctrlClkXTH, TRUE);
- delay1ms(10);
-
- stcPLLCfg.enInFreq = SysctrlPllInFreq6_12MHz; //XTH 8MHz
- stcPLLCfg.enOutFreq = SysctrlPllOutFreq36_48MHz; //PLL 输出
- stcPLLCfg.enPllClkSrc = SysctrlPllXthXtal; //输入时钟源选择XTH
- stcPLLCfg.enPllMul = SysctrlPllMul6; //8MHz x 6 = 48MHz
- Sysctrl_SetPLLFreq(&stcPLLCfg);
-
- ///< 当使用的时钟源HCLK大于24M：设置FLASH 读等待周期为1 cycle(默认值也为1 cycle)
- Flash_WaitCycle(FlashWaitCycle1);
- ///< 使能PLL
- Sysctrl_ClkSourceEnable(SysctrlClkPLL, TRUE);
- ///< 时钟切换到PLL
- Sysctrl_SysClkSwitch(SysctrlClkPLL);
- // ///PCLK时钟分频4分频 12M
- // Sysctrl_SetPCLKDiv(SysctrlPclkDiv4);
- }
已解决
逻辑分析仪采样设置的有问题
速度可以达到6M
|
|
