5本公众号【读芯树:duxinshu_PD】主要介绍数字集成电路物理设计相关知识,才疏学浅,如有错误,欢迎指正交流学习。 这是集成电路物理设计的第六个系列【Physical Verification】的第十二篇文章,本篇文章主要介绍PERC相关内容: 01 — 什么是PERC?
02 — Topology Checker
03 — Layout (LDL) Checker
04 — Current Density Checker
05 — P2P Checker
06 — CNOD Checker
calibre -perc -hier -tyrbo -hyper perc.top ###perc.top LAYOUT SYSTEM GDSII LAYOUT PATH 'design.gds.gz' LAYOUT PRIMARY design PERC NETLIST LAYOUT TEST DEPTH 0 PORT DEPTH 0 PERC REPORT 'perc.rpt' PERC REPORT MAXIMUM ALL PERC REPORT PLACEMENT LIST MAXIMUM ALL PERC REPORT OPTION NO_NET_TYPE NO_DEVICE_PIN DFM DATABASE 'dfmdb' OVERWRITE REVISIONS [ALL] DRC ICSTATION YES LVS EXECUTE ERC NO LAYOUT PROCESS BOX RECORD YES LAYOUT INPUT EXECPTION SEVERITY TESTSTRING_ASTRING 1 LAYOUT INPUT EXECPTION SEVERITY MISSING_REFERENCE 1 LVS SPICE SCALE X PARAMETERS YES INCLUDE './perc.lvs' INCLUDE './perc.rules' 07 — 参考文献
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